3D Integration using Bumpless Wafer-on-Wafer (WOW) Technology
نویسندگان
چکیده
منابع مشابه
Wafer-level 3D integration technology
integration technology S. J. Koester A. M. Young R. R. Yu S. Purushothaman K.-N. Chen D. C. La Tulipe, Jr. N. Rana L. Shi M. R. Wordeman E. J. Sprogis An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as t...
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In this paper we consider the Wafer-to-Wafer Integration problem. A wafer is a p-dimensional binary vector. The input of this problem is described by m disjoints sets (called "lots"), where each set contains n wafers. The output of the problem is a set of n disjoint stacks, where a stack is a set ofm wafers (one wafer from each lot). To each stack we associate a p-dimensional binary vector corr...
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Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration, reduced delay and power dissipation, smaller chip area, etc. Wafer-on-wafer stacking is most attractive for 3D IC fabrication, but it suffers from low compound yield. To improve the compound yield, two efforts have been done in this work. First, a hybrid waf...
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ژورنال
عنوان ژورنال: Journal of the Microelectronics and Packaging Society
سال: 2012
ISSN: 1226-9360
DOI: 10.6117/kmeps.2012.19.4.071